Mind the Gap: Testing AC-Coupled and Differential Interconnects
When the IEEE 1149.1 JTAG standard was first introduced, it changed the way engineers approached PCB testing. For the first time, it allowed full visibility into complex digital boards — without using physical probes.
While 1149.1 works perfectly on DC-coupled, single-ended signals, today’s high-speed designs rely heavily on AC coupling and differential pairs, where the original standard reaches its limits.
To bridge that gap, IEEE 1149.6, released in 2003, introduced new cell types, edge-detecting receivers, and additional test instructions such as EXTEST_PULSE and EXTEST_TRAIN. These innovations make it possible to perform boundary scan tests even on high-speed serial and differential links.
This article looks at where 1149.1 struggles — and how 1149.6 overcomes those challenges to maintain comprehensive test coverage.
A Quick Refresher on IEEE 1149.1
JTAG boundary scan enables engineers to verify PCB interconnects without direct physical access to device pins.
This is achieved by inserting boundary scan cells between the device’s core logic and I/O pads. The cells are connected in a serial scan chain — from TDI (Test Data In) to TDO (Test Data Out) — and can extend across multiple devices on a board.
By shifting data through the chain, a boundary scan controller can instruct devices to drive or sample pin states. This lets you generate known signals or read pin responses without running any firmware — making it an essential tool for hardware validation and production testing.
Why 1149.1 Alone Isn’t Enough
For single-ended, DC-coupled nets, 1149.1 is robust and time-tested. However, it fails to function properly in AC-coupled or differential environments.
AC coupling introduces capacitors that block the steady logic levels 1149.1 depends on. Differential signals pose an additional challenge: both lines must be driven and sensed together, but 1149.1 cells can only handle pins individually.
As a result, detecting faults in high-speed, low-voltage differential links becomes unreliable — limiting test coverage as modern buses like PCIe, SATA, and Ethernet dominate board designs.
IEEE 1149.6: Extending JTAG to Modern Interfaces
IEEE 1149.6 enhances traditional boundary scan to include AC-coupled and differential interconnects. It doesn’t replace 1149.1, but rather extends it with new cell structures, edge-sensitive receivers, and test instructions designed for signal transitions instead of static levels.
Architecture: Cells, Drivers, and Receivers
- Transmit cells can output single pulses or continuous pulse trains instead of steady logic states.
- Receive cells detect signal edges, determining whether transitions occur.
- Differential pairs can be analyzed as two separate legs, allowing the system to identify faults even on one side of the pair.
This architecture ensures that high-speed links can be tested safely and accurately, without disrupting the underlying design.
New Test Instructions: EXTEST_PULSE and EXTEST_TRAIN
IEEE 1149.6 introduces two new JTAG instructions:
- EXTEST_PULSE – sends a single controlled transition across the link.
- EXTEST_TRAIN – transmits a series of transitions for longer or capacitively heavy interconnects.
Instead of monitoring DC levels, the receiving device detects signal transitions: a logical 1 corresponds to a rising edge, while a logical 0 corresponds to a falling edge.
These instructions are fully compatible with the existing 1149.1 command set, allowing seamless testing of boards that mix both DC and AC-coupled nets.
Conclusion
As boards grow faster and more complex, IEEE 1149.6 ensures that boundary scan testing remains relevant. By adding pulse-based drivers and edge-detecting receivers, the standard extends JTAG’s reach into AC and differential domains — areas that 1149.1 alone cannot handle.
The result: greater fault coverage, fewer blind spots, and more reliable validation of high-speed PCB designs.
Design-for-Test (DFT) Tips
Looking to improve your board’s testability?
Make sure your layout supports JTAG access to both 1149.1 and 1149.6 devices, and follow best practices for connecting boundary scan nets to non-JTAG components.
