In the electronics development world, even the most carefully designed prototypes can hide unexpected faults. Recently, during the internal testing of a prototype PCB, a resistive short was detected — a perfect case study to demonstrate how advanced boundary-scan tools can uncover and isolate such issues quickly and precisely.
The board underwent a standard connection test, which immediately flagged a fault: a short circuit between two separate nets. Using a boundary-scan runner interface, the failing test was highlighted in the sequence list (see Figure 1). Expanding the result revealed exactly which pins were involved on the affected nets (Figure 2), giving the test engineer a clear overview before diving into deeper diagnostics.
| Figure 2 – The expanded error, as shown in XJRunner |
By selecting Error Detail, the engineer could review the specific test patterns that detected the fault (Figure 3). For example, in one pattern, the net Controller.SPI1.SCLK was driven low and correctly read back as low, while its counterpart net pin was set to a high-impedance state yet still returned a low reading. On the following test step, when Controller.SPI1.SCLK switched high, the unrelated STACKING net also went high — indicating that an unintended coupling or short was influencing its state.
| Figure 3 |
Because boundary-scan patterns often toggle multiple pins simultaneously to reduce overall test time, the exact cause of such a coupling isn’t always immediately clear. The tool therefore triggered additional targeted tests to pinpoint which net transition caused the unwanted change. In this case, both suspect nets were traced to adjacent pins on the same device package — U1.C10 and U1.D10 — suggesting a possible localized short.
To confirm, the error data was loaded into a Layout Viewer (Figure 4), visually mapping the physical routing of both nets on the PCB. This helped identify where they physically ran close together, increasing the likelihood of a contamination-based fault.
Upon inspection, the root cause was identified as ionic contamination from dried flux residue after assembly, which created a high-resistance path between the pins. An additional ultrasonic cleaning cycle eliminated the problem entirely, as shown in the before-and-after comparison from a similar board (Figure 5).
Interestingly, the short was not a direct zero-ohm connection but a resistive path of roughly 100 kΩ. This meant that conventional driving tests using opposing voltages might have missed it — yet the boundary-scan patterns successfully detected the anomaly. Narrowing the issue down to such a small location also avoided more expensive fault-finding methods such as X-ray inspection or full optical analysis.
In conclusion, this case shows the value of structured, automated boundary-scan testing: detecting faults early, accurately identifying the affected nets and pins, and enabling cost-effective corrective action before the hardware is put into operation. Without such a process, locating this particular defect — especially under a BGA — would have taken significantly more time and effort.
